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SAN JOSE, Calif.--(BUSINESS WIRE)--May 7, 2001-- C Level Design, Inc., the sales and technology leader in hardware design in C/C++, today introduced System Compiler(TM) Designer, a complete design environment for C/C++ hardware design. System Compiler Designer provides users with the most complete C/C++ design environment available, and includes support for C/C++ post-simulation graphical analysis via industry standard VCD waveform viewers, automated regression tests to verify the generated HDL from System Compiler and the CycleC(TM) StyleChecker(TM) analyzer, a powerful compile-time engine that enables designers to develop higher-quality, error-free hardware designs.

``C Level Design is committed to developing the most complete C/C++ based solution for hardware design,'' said Daniel Skilken, president and CEO of C Level Design. ``First, the company delivered the industry's highest performance C/C++ design methodology with CycleC and the first ANSI C/C++ synthesis solution with System Compiler. Now we are expanding the solution to enable HDL designers to leverage the power of C/C++ for hardware design. With this latest release, C Level Design provides the ability for design teams to use C/C++ concurrently with Verilog/VHDL, perform compile-time analysis of the design using the StyleChecker analyzer, debug the design with traditional graphical waveform environments and automate the verification of the results of C/C++ synthesis.''

System Compiler Designer raises the level of productivity for design teams that use C/C++ for hardware design by enabling engineers to use HDL-like features for design and debugging and by automating the task of verifying the post-synthesis results against the original C/C++ design. To facilitate faster and easier design debugging, engineers can now generate value-change-dump (VCD) formatted files during C/C++ simulations, allowing post-simulation analysis using VCD-compliant waveform viewers.

To enable a more ``correct by construction'' approach to coding hardware in C/C++, the StyleChecker analyzer within System Compiler Designer performs a comprehensive compile-time analysis of the C/C++ design, checking for coding violations that would result in inefficient or incorrect HDL output during synthesis. This capability will enable both new and existing C/C++ hardware designers to more rapidly and efficiently create designs using the CycleC methodology.

``One of the key issues for adopting C-based design tools is being able to locate hardware design problems like you do with traditional HDLs,'' said Mike Renault, senior member of Technical Staff at ONEX Communications. ``C Level Design's StyleChecker analyzer is the only tool I have seen that can help me find design errors like inferred latches and incomplete conditional statements, and warns me about coding violations that may result in a functional mismatch between my C++ code and my HDL code. Using C Level's StyleChecker, I can use C++ code just like HDL to design my hardware but simulate 300 times faster.''

Additionally, to help streamline the downstream task of verifying designs after C/C++ synthesis, System Compiler Designer adds the ability to automatically generate a vector-based regression test for HDL generated from System Compiler. Testbench stimulus and result vectors from the C/C++ simulation are saved, and are then replayed through an automatically generated HDL testbench created by System Compiler. The HDL simulation results can then be compared to the results from the C/C++ simulation, with any simulation mismatches automatically flagged.

Pricing and Availability

System Compiler Designer will be available in Q2 2001. Existing System Compiler customers under maintenance will be upgraded at no charge. The U.S. list price for System Compiler Designer is $95,000.

About C Level Design

C Level Design, Inc., the sales and technology leader for C/C++ design tools was founded in 1997 to develop and market system-level design products for system and hardware designers. The company's products and consulting expertise in C/C++ enable global electronics companies in the networking, telecommunications and processor market segments to create and verify their designs using ANSI C/C++ for higher simulation performance and designer productivity, and synthesize those designs for use in their existing RTL HDL design flows. C Level Design is fully committed to supporting industry standards for C/C++ design and is a member of the EDA standards organizations Accellera and VSIA. For more information, visit: http://www.cleveldesign.com

Note to Editors: C Level, CycleC and System Compiler are trademarks of C Level Design, Inc. All other brands or product names may be trademarks or registered trademarks of their respective companies and should be treated as such.

     C Level Design
     David Park, 408/558-7780
     dave@cleveldesign.com
        or
     KJ Communications
     Kella Knack, 650/508-0371
     kjcomk@cs.com